Entity decoder is port ( x : in std_logic_vector (2 down too)

Y : out std_logic_vector ( 0 down to 7 )

VHDL Code for 3x8 Decoder A Decoder is a combinational logic circuit which converts code into a set of signals. It is exactly opposite of Encoder. It is mostly used to generate selection or enable line in a digital circuit. This decoder can be used for decoding any 3-bit code to provide eight outputs, corresponding to eight different combinations of the input code. This is also called a 1 of 8 decoder, since only one of eight output lines is HIGH for a particular input combination. Fig (1): Logic diagram of 3 to 8 decoder.

en : in std_logic) ;

End decoders;

Architecture behavioral of decoder is signal Y 1 : std_logic_vector (7 down to 0) ;

BeginY1 < = “0111 111” when z = “ 000 “ else

“10111111” when x = “001” else

“11011111” when x = “010” else

“11101111” when x = 011” else

“11110111” when x = “100” else

“11111011” when x = “101” else

Vhdl Code For 3 To 8 Decoder Using Case Statement

“11111101” when x = “110” else

“11111110” when x = “111” else

3 To 8 Decoder Vhdl

“11111111” when others;

Y < = y, when en = ‘0’ else “1111 1111” ;

Vhdl Code For 3 To 8 Decoder Using Dataflow Modelling

End behavioral.